Thermal processing is required in the fabrication of silicon and other semiconductor integrated circuits formed in silicon wafers or other substrates such as glass panels for displays. The required temperatures may range from relatively low temperatures of less than 250 degrees C to greater than 1400 degrees C and may be used for a variety of processes such as dopant implant annealing, crystallization, oxidation, nitridation, silicidation, and chemical vapor deposition as well as others.
For the very shallow circuit features required for advanced integrated circuits, it is greatly desired to reduce the total thermal budget in achieving the required thermal processing. The thermal budget may be considered as the total time at high temperatures necessary to complete device fabrication. The time that the wafer needs to stay at the highest temperature can be very short. The greater the total time that the wafer is subject to high temperatures, the more features such as implanted junctions will diffuse and loose their definition. For example, implanted junction depths may become deeper than desired due to diffusion.
Rapid thermal processing (RTP) uses radiant lamps which can be very quickly turned on and off to heat only the wafer and not the rest of the chamber. Pulsed laser annealing using very short (about 20 ns) laser pulses is effective at heating only the surface layer and not the underlying wafer, thus allowing very short ramp up and ramp down rates.
A more recently developed approach in various forms, sometimes called thermal flux laser annealing or dynamic surface annealing (DSA), is described in U.S. Pat. Nos. 7,005,601 and 6,987,240, the disclosures of which are incorporated herein by reference. The DSA system employs many CW diode lasers focused on an extremely narrow (0.07 mm) line beam to produce a very intense beam of light that strikes the wafer as a thin long line of radiation or line beam. The line beam is then scanned over the surface of the wafer in a direction perpendicular to the long dimension of the line beam.
The thinness of the line beam (e.g., 0.07 mm) ensures very short temperature rise and fall times and a short dwell time at the required temperature, e.g., 1300 degrees C, with respect to a fixed location on the wafer surface that is scanned once by the line beam. For example, the temperature of a fixed location on the wafer surface will increase from an ambient 450 degrees C to 1300 degrees C within 0.6 ms, assuming a scan rate within a range of about 50-300 mm/sec is employed. The advantage is that the wafer surface spends an extremely short amount of time at lower or intermediate temperatures (e.g., 500-900 degrees C) at which the higher silicon thermal conductivity promotes heating throughout the wafer and consequent diffusion and loss of underlying circuit feature definition. Instead, the wafer surface spends more time at the desired high temperature (e.g., 1300 degrees C) at which silicon thermal conductivity is lowest for minimum heating of the underlying features, and at which desired effects are maximum (e.g., annealing of implanted dopant impurities, annealing of pre-implant amorphization damage, etc.). The thinness of the line beam corresponds to the minimum resolvable spot size R of the laser beam optical system, which is governed by the following approximate formula:R=λ/2 NA,where λ is the laser wavelength and NA is the numerical aperture of the optics. Numerical aperture is defined as:NA=n sin θ/2,where n is the index of refraction and θ is the angle subtended by the beam between the aperture at the lens and the focal point in a simple or ideal system. In the DSA system referred to above, the wavelength is 810 nm and the angle θ is less than 60 degrees and n is the index of refraction of air (about 1).
These parameters provide a minimum resolvable spot size R corresponding to the small width of the line beam (0.07 mm). Within the preferred beam scanning rate range (50-300 mm/sec), each fixed wafer surface location spends less than about 0.5 ms near the peak temperature (e.g., 1300 degrees C).
The required level of the wafer surface peak temperature (1300 degrees C) requires a power density of about 220 kiloWatts/cm2. To reach this level, the DSA system employs a large number of 810 nm CW diode lasers focused on the same line beam image, as will be described later in this specification.
One problem recently encountered is that some annealing processes requires a longer time at or near the peak temperature (1300 degrees C), than the current dwell time of less than 0.5 ms. This dwell time may be sufficient to cause ion implanted dopant impurities to become substitutional in the semiconductor crystal lattice. However, it may be insufficient to completely cure pre-ion implantation amorphization defects. Pre-ion implantation amorphization is performed prior to ion implantation of dopant impurities to form shallow PN junctions to prevent channeling of the kinetic dopant ions through the crystal lattice below the desired junction depth. Amorphization prevents such channeling by ion bombardment of the wafer with heavier atomic species (oxygen, nitrogen, carbon), causing bombardment damage to at least partially convert the active semiconductor layer from a crystalline state to an amorphous state. The defects in the crystal are cured provided each wafer surface location has a sufficiently long dwell time near 1300 degrees C This may require a dwell time that is longer than the current 0.5 ms dwell time. Furthermore, conversion of the amorphized region back to a crystalline state essentially forms an epitaxial crystalline layer over the bulk crystalline layer, giving rise to another class of defects, namely boundary defects at the interface between the bulk crystal and the re-crystallized surface.
Such boundary defects have been found to be more persistent than the other types of defects, and require a significantly longer dwell time to completely cure or remove, as long as 2 to 3 ms near 1300 degrees C.
In order to provide such a long dwell time, the beam spot size must be enlarged, which essentially broadens the Gaussian profile of the beam intensity along the direction of scan, hereinafter referred to as the “fast axis”. Unfortunately, if the Gaussian beam profile is widened by a given factor, then the slope of the leading edge of the Gaussian beam profile is reduced by approximately the same factor. This increases the temperature rise time (and fall time), thereby subjecting each location on the wafer surface to a longer time at a lower or intermediate temperature, and thus degrading the device structure through thermal diffusion, for example. Thus, widening the beam profile along the fast axis does not appear to be possible. Therefore there is a need for a DSA process in which the boundary defects and other defects in an ion implanted wafer can be annealed without device degradation due to greater thermal diffusion.